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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9600/D Rev. 2, 11/2001
Low Voltage 2.5 V and 3.3 V CMOS PLL Clock Driver
The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. Features: * Multiplication of input frequency by 2, 3, 4 and 6 * Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable * Fully integrated PLL * Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz * Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz * LVCMOS outputs * Outputs disable to high impedance (except QFB) * LVCMOS or LVPECL reference clock options * 48 lead QFP packaging * 50 ps cycle-to-cycle jitter * 150 ps maximum output-to-output skew * 200 ps maximum static phase offset window The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock 48-LEAD LQFP PACKAGE driver. The MPC9600 has the capability to generate clock signals of 50 to CASE 932-03 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN. The MPC9600 is optimized for minimizing the propagation delay between the clock input and FB_IN. Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6. The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels. The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 transmission to VTT=VCC/2. For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of the most demanding systems. The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the reference clock will bypass the PLL. The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.
FA SUFFIX
MPC9600
3.3 V OR 2.5 V LOW VOLTAGE CMOS PLL CLOCK DRIVER
(c) Motorola, Inc. 2001
VCCA
VCC 7
CCLK PCLK PCLK REF_SEL FB_IN FSELA
(pulldown) (pulldn)
0 Ref 1 FB
0
PLL
1
/2 /4
0 1
Bank A
D Q
QA0 QA1 QA2 QA3 QA4 QA5
Vcc/2 (pullup) (pulldown) (pullup)
/8 200 - 400 MHz /12
0 1 (pullup) 0 1 (pullup) 0 1 (pullup) (pulldown)
Bank B
D Q
QA6 QB0-6
7
FSELB
Bank C
D Q
QC0-6
7
FSELC
Feedback
D Q
QFB
FSEL_FB OE
8
GND
Figure 1. MPC9600 Logic Diagram
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TIMING SOLUTIONS
PIN CONFIGURATION
Pin PCLK, PCLK CCLK FB_IN QAn QBn QCn QFB REF_SEL FSELA FSELB FSELC FSEL_FB OE VCCA VCC GND I/O Input Input Input Output Output Output Output Input Input Input Input Input Input Type PECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Power supply Power supply Ground GND QFB Description Differential reference clock frequency input Reference clock input PLL feedback clock input Bank A outputs Bank B outputs Bank C outputs Differential feedback output Reference clock input select Selection of bank A output frequency Selection of bank B output frequency Selection of bank C output frequency Selection of feedback frequency Output enable Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA Core power supply Ground GND VCC VCC 25 24 23 22 21 20 19 GND QC0 QC1 QC2 VCC QC3 QC4 GND QC5 QC6 OE VCC 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 GND QB0 QB1 QB2 QB3 QB4 QB5 27 FSELB QB6 26 FSELC
36 VCC QA6 QA5 QA4 GND QA3 QA2 VCC QA1 QA0 FB_IN GND 37 38 39 40 41 42
35
34
33
32
31
30
29
28
MPC9600
43 44 45 46 47 48
CCLK
REF_SEL
FSEL_FB
VCCA
PCLK
PCLK
GND
VCC
Figure 2. 48 Lead Package Pinout (Top View)
TIMING SOLUTIONS
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FSELA
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FUNCTION TABLE (CONTROLS)
Control Pin REF_SEL VCCA OE FSELA FSELB FSELC FSEL_FB 0 CCLK PLL Bypass1 Outputs Enabled Output Bank A at VCO/2 Output Bank B at VCO/2 Output Bank C at VCO/2 Feedback Output at VCO/8 1 PCLK PLL Power Outputs Disabled (except QFB) Output Bank A at VCO/4 Output Bank B at VCO/4 Output Bank C at VCO/4 Feedback Output at VCO/12
1..VCCA = GND, PLL off and bypassed for static test and diagnosis
Table 1: ABSOLUTE MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Parameter Min -0.3 -0.3 -0.3 Max 4.6 VCC + 0.3 VCC + 0.3 20 50 Unit V V V mA mA
TStor Storage Temperature Range -40 125 C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
Table 2: GENERAL SPECIFICATIONS
Symbol VTT MM HBM CDM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) ESD Protection (Charged Device Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 400 4000 1500 200 10 4.0 Min Typ VCC
B2
Max
Unit V V V V mA pF pF
Condition
Per output Inputs
Table 3: DC CHARACTERISTICS (VCC = 3.3 V 5%, TA = -40 to +85C)
Symbol VIH VIL VPP VCMRa VOH VOL ZOUT IIN ICCA Characteristics Input High Voltage Input Low Voltage Peak-to-peak Input Voltage (DC) Common Mode Range (DC) Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current 2.0 14 - 17 150 5.0 PCLK, PCLK PCLK, PCLK 250 1.0 2.4 0.55 0.30 VCC-0.6 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V mV V V V V Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-24 mAb IOL= 24mA IOL= 12mA
W
A mA VIN = VCC or GND VCCA Pin
ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. The MPC9600 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
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Table 4: DC CHARACTERISTICS (VCC = 2.5 V 5%, TA = -40 to +85C)
Symbol VIH VIL VPP VCMRa VOH VOL ZOUT IIN ICCA Characteristics Input High Voltage Input Low Voltage Peak-to-peak input voltage (DC) Common Mode Range (DC) Output High Voltage Output Low Voltage Output Impedance Input Leakage Current Maximum PLL Supply Current 3.0 17 - 20 150 5.0 PCLK, PCLK PCLK, PCLK 250 1.0 1.8 0.6 VCC-0.6 Min 1.7 Typ Max VCC + 0.3 0.7 Unit V V mV V V V Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-15 mAb IOL= 15 mA
W
A mA
VIN = VCC or GND VCCA Pin
ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. The MPC9600 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
Table 5: AC CHARACTERISTICS (VCC = 3.3 V 5% or VCC = 2.5 V 5%, TA = -40 to +85C)a
Symbol fref Input Frequency Characteristics Min 25 16.67 0 200 Typ Max 50 33 500 400 200 100 75 1000 VCC-0.8 VCC-0.6 1.0 -60 +30 +40 +130 70 70 30 40 30 45 0.1 50 +140 +230 150 150 75 125 75 55 1.0 10 10 Unit MHz MHz MHz MHz MHz MHz % mV V V ns ps ps ps ps ps ps ps % ns ns ns MHz MHz -3 dB point of PLL transfer characteristic see Figure 12 LVPECL LVPECL LVPECL see Figure 12 PLL locked PLL locked Measured at coincident rising edge PLL locked PLL locked Condition PLL locked PLL locked VCCA = GND
B8 feedback (FSEL_FB=0) B12 feedback (FSEL_FB=1)
Static test mode (VCCA = GND)
fVCO fMAX
VCO Frequency Maximum Output Frequency
B2 outputs (FSELx=0) B4 outputs (FSELx=1)
PCLK, PCLK
100 50 25 500 1.2 1.2
frefDC VPP VCMRb
Reference Input Duty Cycle Peak-to-peak Input Voltage
Common Mode Range PCLK, PCLK (VCC = 3.3 V 5%) PCLK, PCLK (VCC = 2.5 V 5%) CCLK Input Rise/Fall Time Propagation Delay (static phase offset) CCLK to FB_IN PECL_CLK to FB_IN Output-to-output Skew all outputs, single frequency all outputs, multiple frequency within QAx output bank within QBx outputs within QCx outputs
tr, tf t()
tsk(o)
DC tr, tf tPLZ, HZ tPZL, ZH BW
Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time PLL Closed Loop Bandwidth
B8 feedback (FSEL_FB=0) B12 feedback (FSEL_FB=1)
5
1.0 - 10 0.6 - 4.0
TIMING SOLUTIONS
MOTOROLA
Table 5: AC CHARACTERISTICS (VCC = 3.3 V 5% or VCC = 2.5 V 5%, TA = -40 to +85C)a
Symbol tJIT(CC) Characteristics Cycle-to-cycle Jitterc All outputs in All outputs in tJIT(PER) Period Jitterc All outputs in All outputs in tJIT() I/O Phase Jitter (1 s) Min Typ 40 40 Max 130 180 Unit ps ps Condition See application section for other configurations See application section for other configurations RMS value at fVCO=400MHz
B2 configuration B4 configuration B2 configuration B4 configuration
VCC = 3.3V VCC = 2.5V
25 20
70 100 17d 15c
ps ps ps ps
tLOCK Maximum PLL Lock Time 5.0 ms a. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC characteristics apply for parallel output termination of 50 to VTT. b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(). c. Cycle-to-cycle and period jitter depends on output divider configuration. d. See applications section for max I/O phase jitter versus frequency.
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configurations, the table describes the outputs using the input clock frequency CLK as a reference. Programming the MPC9600 The feedback divider division settings establish the output relationship, in addition, it must be ensured that the VCO will The MPC9600 clock driver outputs can be configured into be stable given the frequency of the outputs desired. The several divider modes. Additionally the external feedback of feedback frequency should be used to situate the VCO into a the device allows for flexibility in establishing various input to frequency range in which the PLL will be stable. The design output frequency relationships. The selectable feedback of the PLL supports output frequencies from 50 MHz to 200 divider of the three output groups allows the user to configure MHz while the VCO frequency range is specified from 200 the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency MHz to 400 MHz and should not be exceeded for stable ratios. The use of even dividers ensure that the output duty operation. cycle is always 50%. Table 6 illustrates the various output Table 6: Output Frequency Relationshipa for QFB connected to FB_IN
APPLICATIONS INFORMATION
Configuration Inputs FSEL_FB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FSELA 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSELB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FSELC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Input Frequency Range CLK [MHz]
Output Frequency Ratio and Range Ratio, QAx [MHz] 4SCLK 4SCLK 4SCLK (100-200) (100-200) (100-200) (100-200) (50.0-100) (50.0-100) (50.0-100) (100-200) (100-200) (100-200) (100-200) (50.0-100) (50.0-100) (50.0-100) (50.0-100) Ratio, QBx [MHz] 4SCLK 4SCLK 2SCLK 2SCLK 4SCLK 4SCLK 2SCLK 2SCLK 6SCLK 6SCLK 3SCLK 3SCLK 6SCLK 6SCLK 3SCLK 3SCLK (100-200) (100-200) (50.0-100) (50.0-100) (100-200) (100-200) (50.0-100) (50.0-100) (100-200) (100-200) (50.0-100) (50.0-100) (100-200) (100-200) (50.0-100) (50.0-100) Ratio, QCx [MHz] 4SCLK 2SCLK 4SCLK 2SCLK 4SCLK 2SCLK 4SCLK 2SCLK 6SCLK 3SCLK 6SCLK 3SCLK 6SCLK 3SCLK 6SCLK 3SCLK (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100) (100-200) (50.0-100)
25.0-50.0
4SCLK 2SCLK 2SCLK 2SCLK 6SCLK 6SCLK 6SCLK
2SCLK (50.0-100)
16.67-33.33
6SCLK 3SCLK 3SCLK 3SCLK 3SCLK
a. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200-400.
Typical and Maximum Period Jitter Specification
Device Configuration All output banks in or divider configurationa (FSELA=0 and FESLB=0 and FSELC=0) (FSELA=1 and FESLB=1 and FSELC=1) Mixed divider configurationsb for output banks in divider configurations for output banks in divider configurations QA0 to QA6 Typ 25 20 80 25 Max 50 70 130 70 QB0 to QB6 Typ 50 50 100 60 Max 70 100 150 100 QC0 to QC6 Typ 25 20 80 25 Max 50 70 130 70
B2 B4 B2/B4
B2 B4
B2 B4
a. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 1 for an example configuration. b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. See Figure 2 for an example.
Typical and Maximum Cycle-to-cycle Jitter Specification
Device Configuration All output banks in or divider configurationa (FSELA=0 and FESLB=0 and FSELC=0) (FSELA=1 and FESLB=1 and FSELC=1) Mixed divider configurationsb for output banks in divider configurations for output banks in divider configurations QA0 to QA6 Typ 40 40 150 30 Max 90 110 250 110 QB0 to QB6 Typ 80 120 200 120 Max 130 180 280 180 QC0 to QC6 Typ 40 40 150 30 Max 90 110 250 110
B2 B4 B2/B4
B2 B4
B2 B4
a. In this configuration, all MPC9600 outputs generate the same clock frequency. b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately.
TIMING SOLUTIONS
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Figure 3. Configuration for 125 MHz clocks
fref = 20.833 MHz CCLK QA0-6 7 QB0-6 FB_IN 1 0 0 0 FSEL_FB FSELA FSELB FSELC MPC9600 20.833 MHz (Feedback) Frequency range Input QA outputs QB outputs QC outputs Min 16.67 MHz 100 MHz 100 MHz 100 MHz Max 33.33 MHz 200 MHz 200 MHz 200 MHz QC0-6 7 QFB 7 125 MHz 125 MHz 125 MHz
Figure 4. Configuration for 133.3/66.67 MHz clocks
fref = 33.33 MHz CCLK QA0-6 7 QB0-6 FB_IN 0 0 1 1 FSEL_FB FSELA FSELB FSELC MPC9600 33.33 MHz (Feedback) Frequency range Input QA outputs QB outputs QC outputs Min 25 MHz 100 MHz 100 MHz 100 MHz Max 50 MHz 200 MHz 200 MHz 200 MHz QC0-6 7 QFB 7 66.67 MHz 66.67 MHz 133.3 MHz
Power Supply Filtering The MPC9600 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9600 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9600. Figure 5. illustrates a typical power supply filter scheme. The MPC9600 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325 V (VCC=3.3 V or VCC=2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 5. "VCCA Power Supply Filter" must have a resistance of 9-10 (VCC=2.5 V) to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 5. "VCCA Power Supply Filter", the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB.
RF = 9-10 for VCC = 2.5 V or VCC = 3.3 V CF = 22 F for VCC = 2.5 V or VCC = 3.3 V RF VCC CF 10 nF VCCA MPC9600 VCC 33...100 nF
W
Figure 5. VCCA Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9600 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs.
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TIMING SOLUTIONS
Using the MPC9600 in zero-delay applications Nested clock trees are typical applications for the MPC9600. For these applications the MPC9600 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100ES6111 or MC100ES6226, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC9600 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9600 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9600 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t()), I/O jitter (tJIT(), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. Calculation of part-to-part skew The MPC9600 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (CCLK or PCLK) of two or more MPC9600 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is:
Table 8: Confidence Facter CF
CF 1s 2s 3s 4s 5s 6s Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999
The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -261 ps to 341 ps relative to CCLK (VCC=3.3V and fVCO = 200 MHz):
tSK(PP) = tSK(PP) =
[-60ps...140ps] + [-150ps...150ps] + [(17ps @ -3)...(17ps @ 3)] + tPD, LINE(FB) [-261ps...341ps] + tPD, LINE(FB)
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter:
Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC9600). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 7. can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP).
TCLKCommon
-t()
tPD,LINE(FB)
QFBDevice 1
tJIT()
Any QDevice 1
+tSK(O) +t()
Figure 7. Max. I/O Jitter versus VCO frequency for VCC=2.5V and VCC=3.3V Driving Transmission Lines The MPC9600 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel
QFBDevice2
tJIT()
Any QDevice 2 Max. skew
+tSK(O) tSK(PP)
Figure 6. MPC9600 max. device-to-device skew Due to the statistical nature of I/O jitter a RMS value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8.
TIMING SOLUTIONS
9
MOTOROLA
terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9600 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9600 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9600 OUTPUT BUFFER IN
14
= 50 || 50 = 36 || 36 = 14 = 3.0 ( 25 / (18+17+25) = 1.31 V At the load end the voltage will double due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Z0 RS R0 VL
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
RS = 36
ZO = 50 OutA
1.0 MPC9600 OUTPUT BUFFER IN
14
RS = 36
ZO = 50 OutB0
0.5
0 RS = 36 ZO = 50 OutB1 2 4 6 8 TIME (nS) 10 12 14
Figure 9. Single versus Dual Waveforms Figure 8. Single versus Dual Transmission Lines The waveform plots in Figure 9. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9600 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9600. The output waveform in Figure 9. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9600 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 10. Optimized Dual Line Termination
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TIMING SOLUTIONS
The Following Figures Illustrate the Measurement Reference for the MPC9600 Clock Driver Circuit
MPC9600 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50
W
RT = 50 VTT
RT = 50 VTT
Figure 11. CCLK MPC9600 AC test reference
Differential Pulse Generator Z = 50
ZO = 50
MPC9600 DUT ZO = 50
W
RT = 50 VTT
RT = 50 VTT
Figure 12. PCLK MPC9600 AC test reference
PCLK PCLK VPP VCMR VCC VCC CCLK VCC VCC VCC VCC
B2 B2
GND
FB_IN t()
B2
FB_IN
GND t()
GND
Figure 13. Propagation delay t(), static phase offset) test reference
VCC VCC tP T0 DC = tP /T0 x 100%
Figure 14. Propagation delay t() test reference
VCC VCC VCC VCC
B2
B2 B2
GND
GND
GND tSK(O)
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device
Figure 15. Output Duty Cycle (DC)
Figure 16. Output-to-output Skew tSK(O)
TIMING SOLUTIONS
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TN
TN+1
TJIT(CC) = |TN -TN+1 |
T0
TJIT(P) = |TN -1/f0 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles
Figure 17. Cycle-to-cycle Jitter
Figure 18. Period Jitter
CCLK (PCLK) FB_IN VCC=3.3 V 2.4 0.55 TJIT() = |T0 -T1 mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles tF tR VCC=2.5 V 1.8 V 0.6 V
Figure 19. I/O Jitter
Figure 20. Output Transition Time Test Reference
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TIMING SOLUTIONS
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 932-03 ISSUE F
0.200 AB T-U Z 9 A1
48 37
4X
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8.MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9.EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0_ 7_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M_
TOP & BOTTOM
R
GAUGE PLANE
0.080
SECTION AE-AE
TIMING SOLUTIONS
EEE CCC EEE CCC EEE CCC
F D
M
C
E
AC T-U Z H DETAIL AD AA W K L_
13
0.250
N
J
MOTOROLA
NOTES
MOTOROLA
14
TIMING SOLUTIONS
NOTES
TIMING SOLUTIONS
15
MOTOROLA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2001.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
MOTOROLA
16
MPC9600/D TIMING SOLUTIONS

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